Job description
Our client is one of the world’s largest and most successful IC Design Semiconductor/Wafer Fabrication company. They provide the ultimate in pioneering IC technology to create unique and innovative designs for a broad range of high-tech applications.
They are currently seeking a skilled Design-For-Test (DFT) Engineer to join their team as a Senior / DFT Engineer, you will be responsible for providing design for test support to internal RD groups across a wide range of application.
Responsibilities:
- Collaborate closely with IC Design team.
- Engage with design team to discuss and extend specifications, particularly with respect to test insertion and test pattern generation.
- Develop test plans and implement design-for-test structures (At-speed test, MBIST, test compression, boundary scan), with a strong background in hierarchical DFT flow.
- Create or modify scan constraints.
- Generate ATPG vectors for various fault models and scan fsdb for IR analysis.
- Perform functional and ATPG pre and post layout simulations.
- Improve the internal scripting environment based on acquired knowledge.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering or a related field.
- Proven experience in DFT and ASIC synthesis, with a focus on design-for-test structures.
- Familiarity with industry standard EDA tools, such as Synopsys, Cadence, or Mentor Graphics.
- Proficiency in scripting languages, such as TCL or Perl.
- Excellent verbal and written communication skills, with the ability to clearly convey technical concepts.
